Today's VLSI products are extremely complex in microarchitecture, circuit design and fabrication process. For a microprocessor with millions of transistors, it is almost impossible to prove that each was manufactured correctly without a proper testing strategy. Therefore, high performance high speed microprocessors demand much more efficient and effective testing technology than ever. In addition, the increasingly complex test methods require that designers comply with some test design rules when developing novel microarchitectures for their chips.
Digital circuits are tested using a variety of strategies including functional test patterns, deterministic structural test patterns, and random patterns. Random pattern testing is particularly significant because it requires relatively little test data and can be accomplished not only by automated test equipment, but by the digital circuit itself using Built-in Self Test (BIST) circuitry. In order to achieve high random pattern testability, it is often necessary to modify a digital circuit design such that random patterns more easily detect potential defects in the IC under test.
One technique for testing digital circuits is known as scan chains. With scan chains, testing is made easier by setting and observing every flip flop in an integrated circuit. A special signal normally referred to as scan enable is added to a design. When this signal is applied, each flip flop in the design is connected into a long shift register. One input pin is provided to feed data to the chain of flip flops, and one output pin is connected to the output of the chain of flip flops. By using the chip's clock signal, an arbitrary pattern can be entered into the chain of flip flops and the state of each flip flop can be read out. When a full scan design is being used, automatic test pattern generation is easy to implement. No sequential pattern generation is required and combinatorial tests can be used.
The added scan chain circuitry simplifies the application of manufacturing tests to a final product and can be used to validate intended behavior of a design and ensure that the product does not have defects.
The testing process can be performed manually during the design stage of the integrated circuit, or automatically when converting a design specification into an interconnection of transistors that define a final semiconductor product.
The testing may target either the functional or structural properties of an integrated circuit. In functional testing, an attempt is made to validate that the final product operates correctly, and its behavior is consistent with the original specification or its constrained specification. When targeting structural properties, design functions of the integrated circuit are not addressed. Instead, testing is performed at selected design points to determine if a circuit was manufactured correctly, or a design behaves correctly at isolated subset of points. In current design methodologies, structural testing is limited in practice due to difficulty of accessing tap points and limitations of test equipment.
Integrated circuits are tested using a variety of strategies including functional test patterns, deterministic structural test patterns, and random patterns. Random pattern testing is particularly significant because it requires relatively little test data and can be accomplished not only by automated test equipment, but by the circuit itself using Built-in Self Test (BIST) circuitry. In order to achieve high random pattern testability, it is often necessary to modify a digital circuit design such that random patterns more easily detect potential defects in the IC under test.
One way of modifying digital circuits to provide improve random pattern testability using reachable states is known as test point insertion. During test point insertion, additional logic and scannable latches are added to the logic to provide additional points of control or observation during testing. Referring to FIG. 1, there is shown a prior art random-resistant circuit which exhibits poor toggling activity due to addition of wide AND gates 112, 114, 116, 118 coupled to existing latches 120 and having respective outputs connected as inputs to an AND gate 22. A test enable signal is used to activate logic needed in a testing mode. Activation is performed by setting the signal value, (e.g., a Test Enable signal), to, for example, a logic 1 state, which activates AND gate 122, and in turn enables control-improving logic.
Referring to FIG. 2, a logic circuit 202 is inserted between the output of AND gates 212, 214, 216 and 218 and the input terminals of AND gate 222. The signal feeding the input terminals 224 of a four input AND gate 222 are nearly always 0 when random patterns are applied to the circuit, since each input AND gate 212, 214, 216, 218 will produce a logic 1 very infrequently. Such a path is rarely sensitized to allow faults to propagate through downstream AND gate 22. Furthermore, faults in the downstream logic that require logic 1 for activation will rarely be activated. If, however, a control 1 test point is added to the circuit, the random pattern testability substantially improves.
Continuing with FIG. 2, adding OR gates 230, 232, 234, 236 driven by a latch that can be scanned will improve the probability that logic 1's will appear on the inputs to the four input AND gate 222, and will propagate to downstream logic to enable the detection of certain faults not otherwise tested. Additional faults will be allowed to propagate through the four inputs of the AND gate 222, and faults located in downstream logic requiring a logic 1 for activation will have a much higher probability of being activated. OR gates 230, 232, 234, 236 which are driven by scannable latch 238 implemented as AND gates 241 and having one input of each tied to a test enable signal is known as a control 1 test point. In other cases, a control 0 test point (implemented as an AND gate) or an observation point (implemented as a signal feeding a scannable latch) may be inserted. It is understood that additional latches (not shown) have to be respectively added to the design to provide the other control input signal to each respective AND gate 241 for testing purposes.
Most integrated circuit designs have states that are never reached in the functional mode, i.e., in normal execution.